1. Field of Invention
The field of this invention is related to semiconductor processing and in particular making wafer alignment marks clear and concise throughout the many steps of wafer processing.
2. Description of Related Art
Several wafer alignment strategies exist using different patterns and locations to achieve the alignment of a semiconductor wafer to a mask containing an image to be transferred to the wafer. These strategies vary from alignment marks located between shot sites (also known as chip sites) to global alignment marks located in two shot sites near the peripheral of the wafer. There are also global strategies in which the alignment marks are located between shot sites in the more peripheral regions of the wafer. Care must be given to maintaining the integrity of these alignment marks to provide adequate alignment of masks to the semiconductor wafer throughout the processing of the wafer so as to provide the best possible device yield.
In U.S. Pat. No. 5,695,897 (Mitome et al.) an alignment method is described in which a first stepper having a first magnification reduction and a second stepper having a second magnification are used. The first stepper is used for global alignment and the second stepper is used in relation with each individual shot site. The alignment marks are located between shot sites. In U.S. Pat. No. 5,442,445 (Tatsuno et al.) is described an alignment method for registering a target with respect to a predetermined reference position. This system uses a registration marks formed on the target object. In U.S. Pat. No. 4,778,275 (van den Brink et al.) a method of aligning a mask pattern with a substrate is described. Two alignment marks are used by two separate alignment systems which are each associated with one alignment mark. In U.S. Pat. No. 4,657,379 (Suwa) describes a method and exposure mask to perform alignment of the mask to a wafer without decreasing throughput. A pair of mark regions contain alignment marks that cross the mark region. The alignment mark regions are located at two sides of the pattern region of the mask image. In the “Handbook of Microlithography, Micromachining and Microfabrication”, edited by P. Rai Chaudhury, Copublished by The international Society for Optical Engineering and The Institute of Electrical Engineers, 1997, page 96 discusses the ASM-L stepper which uses a zero layer alignment strategy that uses alignment marks etched directly into bare silicon before any other processing.
A global alignment system, similar to the ASM-L alignment system, is the focus of this invention. The global alignment system is a simple strategy to implement and has high throughput, but requires an extra processing step. The zero layer alignment marks are small 10×8 mm and occupy only a small portion of a shot site. The shot site containing the zero layer alignment marks is blank other than the alignment marks and provides a different topology to the surrounding shot sites which have full circuit images. This difference in topology causes yield problems ranging from loading problems with photoresist and etch to bad focus errors caused by the topology over the mark region from processing the wafer.